As portable electronic equipment continues its double-digit percentage growth each year while battery technology is only projected to improve by 30% over the next five years, there is a tremendous demand for low-power design solutions to bridge this technology gap. This problem is further aggravated by the fact that microprocessor on-chip clock rates are continually increasing, leading to a substantial increase in dynamic switching power consumption.
From its introduction, CMOS technology emerged as the one technology with extremely low static power dissipation. In a typical CMOS gate, most of the power dissipation is dynamic power dissipation associated with the switching of the gate from one logic state to the other. The dynamic power dissipation of a CMOS gate includes two components, capacitive power dissipation due to the charging and discharging of the total load capacitance at the output of the CMOS gate, and short-circuit power caused by the flow of through or short-circuit current through the CMOS gate from the power supply to ground.
FIG. 1 illustrates an exemplary CMOS inverter. As shown in FIGS. 1 and 2, when the CMOS inverter of FIG. 1 switches between its logic states, there is a time period during which both the p-MOSFET and the n-MOSFET conduct and thus create a direct path from the power supply to ground, permitting the flow of short-circuit current I.sub.sc, thereby resulting in short-circuit power dissipation. In particular, from the point in time when the input voltage of the inverter reaches the switching threshold voltage V.sub.tn of the n-MOSFET until the point in time when the input voltage reaches the threshold voltage V.sub.tp of the p-MOSFET, both the n-MOSFET and the p-MOSFET are conductive, thus permitting the short-circuit current I.sub.sc to flow.
The total dynamic power dissipation of a CMOS gate depends upon a number of factors such as the load capacitance at the output of the CMOS gate, the strength of the CMOS gate, the switching speed of the CMOS gate, etc. Any low power solution involves optimization of one or more of these factors in order to minimize power dissipation.
The present invention provides a low power CMOS circuit design technique wherein the gate strength of a given CMOS gate is selected by considering its input slew and its output load conditions. The technique can be applied to the non-speed critical paths in a CMOS circuit in order to reduce overall power dissipation without sacrificing circuit throughput.